Diferenças entre edições de "Streaming SIMD Extensions"

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'''SSE''' ('''S'''treaming [[SIMD|'''S'''IMD]] '''E'''xtensions, originallyinicialmente calledchamado de '''ISSE''', '''I'''nternet '''S'''treaming '''S'''IMD '''E'''xtensions) isé aum [[SIMD]] (Single Instruction, Multiple Data) [[instructionconjuntos setde instruções]] designeddesenvolvido bypela [[Intel]] ande introducedintroduzido inno mercado em 1999 inno theirprocessador [[Pentium III]] seriescomo processorsresposta asà a reply totecnologia [[AMD3DNow!]]'s da [[3DNow!AMD]] (whichque hadfoi debutedlançada aum yearano earlierantes).
 
O SSE containscontém 70 newnovas instructionsinstruções.
 
ItEle wasfoi originallyoriginalmente knownconhecido ascomo '''KNI''' for '''''K'''atmai '''N'''ew '''I'''nstructions'' (''Katmai'' wasera theo codeapelido namepara foro the firstprimeiro Pentium III core(com núcleo revisionrevisto). DuringDurante theo projeto Katmai projecta Intel wasprocurava lookingdistingui-lo toda distinguishsua itlinha fromanterior theirde earlier product lineprodutos, particularlyparticularmente theirdo flagshipprojeto [[Pentium II]]. A AMD eventuallyrapidamente addedaproveitou supportdo forprojeto da Intel SSEe instructionsadicionou suporte às instruções SSEs, startingcomeçando assim witha itsera do famoso processador [[Athlon XP]] processor.
 
A Intel desapontou-se com seu primeiro esforço de desenvolvimento '''SIMD''' o [[IA-32]] e o [[MMX]]. MMX possuía dois grandes problemas: ele re-utilizava [[pontos de flutuação]] registrados, fazendo com que a [[CPU]] ficasse impossibilitada de trabalhar em ambos '''Ponto de flutuação''' e instruções SIMD ao mesmo tempo, só funcionava com intruções simples.
Intel was generally disappointed with their first [[IA-32]] SIMD effort, [[MMX]]. MMX had two main problems: it re-used existing [[floating point]] registers making the [[Central processing unit|CPU]] unable to work on both [[floating point]] and SIMD data at the same time, and it only worked on [[integers]].
 
SSE adds eight new 128-bit registers known as XMM0 through XMM7. Each register packs together four 32-bit [[single-precision]] floating point numbers.
The first CPU to support SSE, the Pentium III, shared execution resources between SSE and the [[floating point unit|FPU]]. While a compiled application can interleave FPU and SSE instructions side-by-side, the Pentium III will not issue a FPU and a SSE instruction in the same clock-cycle. This limitation reduces the effectiveness of [[Instruction pipeline|pipelining]], but the separate XMM registers do allow SIMD and scalar floating point operations to be mixed without the performance hit from explicit MMX/floating point mode switching.
 
==LaterVersões Versionsposteriores==
 
*'''[[SSE2]]''', introduced with the [[Pentium 4]], is a major enhancement to SSE (which some programmers renamed "SSE1"). SSE2 adds new math instructions for [[double-precision]] (64-bit) floating point and 8/16/32-bit integer data types, all operating on the same 128-bit XMM vector register-file previously introduced with SSE. SSE2 enables the programmer to perform SIMD math of virtually any type (from 8-bit integer to 64-bit float) entirely with the XMM vector-register file, without the need to touch the (legacy) MMX/FPU registers. Many programmers consider SSE2 to be "everything SSE should have been", as SSE2 offers an orthogonal set of instructions for dealing with common datatypes.
*'''[[SSE4]]''' is another major enhancement, adding a dot product instruction, lots of additional integer instructions, a popcnt instruction, and more. There are currently no CPU:s on the market that implement SSE4, but it's coming. An overview can be found at http://www.intel.com/technology/architecture/new_instructions.htm .
 
==See also==
*[[MMX]]
*[[3DNow!]]
*[[AltiVec]]
*[[Pentium III#Pentium_III.27s_SSE_Implementation|Pentium III's SSE Implementation]]
 
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[[Categoria:Processadores]]
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